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Obed K. Allotey Babington · Peerford

Ashesi University / Scholars

OB

Obed K. Allotey Babington

Ashesi University

Publishing since 2025, latest 2026

Computer Vision and Pattern Recognition
Hardware and Architecture
Computational Theory and Mathematics
Electrical and Electronic Engineering

Their record on OpenAlex
Download CV:PDF Word
Who they write with Where their co-authors are Every publication
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Publications: 32025–2026
Citations: 1to those papers
h-index: 1i10-index 0
Field-weighted impact: 0.471.00 is the world average
World top 10%: 0%0 of 2 scored papers
Open access: 0%0 papers free to read

By year

Papers, and the citations to them

Publications, left axisCitations to that year’s papers, right axis2026 still in progress

Citations received each year

Peerford

To all their work, old papers included. Google Scholar also counts citations from theses, books and web pages, so its line runs higher.

What they work on

From the classification of each paper

Subfields

Computer Vision and Pattern Recognition267%
Hardware and Architecture267%
Computational Theory and Mathematics

Publications

3 in all

Newest Most cited Oldest Title

Search their publications by title

Micro-Architectural Evaluation of an FPGA-Based LSTM Accelerator
2026PublicationFirst author0 citations10.1109/mlise70044.2026.11607610
On-Chip vs. Off-Chip FPGA Acceleration for Embedded Neural Networks
2025PublicationFirst author1 citation10.1109/iemecon69302.2025.11365896

133%

Electrical and Electronic Engineering133%

Physical Sciences

Topics most written on

Advanced Neural Network Applications2
Embedded Systems Design Techniques2
Advanced Memory and Neural Computing1
Numerical Methods and Algorithms1

Who they write with

Their most frequent co-authors, and the papers those co-authors share

How it can be read

0% free to read

Closed 3 · 100%Behind a paywall

Most cited

On-Chip vs. Off-Chip FPGA Acceleration for Embedded Neural Networks
20251 citation
Micro-Architectural Evaluation of an FPGA-Based LSTM Accelerator
20260 citations
An FPGA-Based Hardware-Software Co-Design Approach for Embedded Machine Learning Acceleration
20250 citations

An FPGA-Based Hardware-Software Co-Design Approach for Embedded Machine Learning Acceleration

2025PublicationFirst author0 citations10.1109/mcsoc67473.2025.00117